MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 141

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

2.3.12
Freescale Semiconductor
PJ1
PJ0
PAD15
PAD14
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Pins AD15-0
To activate the digital input function the related bit in the ADC Digital Input
Enable Register (ATDDIEN) must be set to 1. If the ADC is routed to port
C the input buffers are automatically enabled on the freed up port AD pins.
Additionally on pins shared with ACMPM and ACMPP the ACDIEN bit
must be set to 1 in the ACMP Control Register (ACMPC).
• Except 20 TSSOP and 32 LQFP: The SPI1 MOSI signal is mapped to this pin when used with the SPI
• 48 LQFP: The TIM channel 6 signal is mapped to this pin when used with the timer function. The TIM
• Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode.
• Signal priority:
• Except 20 TSSOP and 32 LQFP: The SPI1 MISO signal is mapped to this pin when used with the SPI
• 48 LQFP: The PWM channel 6 signal is mapped to this pin when used with the PWM function. The
• Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode.
• Signal priority:
• 64/100 LQFP: The unbuffered analog output signal DACU0 of the DAC0 module is mapped to this pin
• 64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN15
• 64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode.
• Signal priority:
• 64/100 LQFP: The non-inverting analog input signal AMPP0 of the DAC0 module is mapped to this pin
• 64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN14
• 64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode.
• Signal priority:
function. Depending on the configuration of the enabled SPI1 the I/O state is forced to be input or
output.
forces the I/O state to be an output for a timer port associated with an enabled output.
48 LQFP: MOSI1 > IOC6 > GPO
64/100 LQFP: MOSI1 > GPO
function. Depending on the configuration of the enabled SPI1 the I/O state is forced to be input or
output.
enabled PWM channel forces the I/O state to be an output.
48 LQFP: MISO1 > PWM6 > GPO
64/100 LQFP: MISO1 > GPO
if the DAC is operating in “unbuffered DAC” mode. If this pin is used with the DAC then the digital I/O
function and pull device are disabled.
and the related digital trigger input are mapped to this pin. The ADC function has no effect on the
output state. The input buffer is controlled by the related ATDDIEN bit and the ADC trigger function.
64/100 LQFP: DACU0 > GPO
if the DAC is operating in “unbuffered DAC with operational amplifier” or “operational amplifier only”
mode. If this pin is used with the DAC then the digital input buffer is disabled.
and the related digital trigger input are mapped to this pin. The ADC function has no effect on the
output state. The input buffer is controlled by the related ATDDIEN bit and the ADC trigger function.
64/100 LQFP: GPO
Table 2-15. Port
MC9S12G Family Reference Manual, Rev.1.01
Table 2-16. Port
J
NOTE
Pins PJ7-0 (continued)
AD
Pins AD15-8
Port Integration Module (S12GPIMV0)
141