MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 380
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MC9S12G
Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12G.pdf
(1160 pages)
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Analog-to-Digital Converter (ADC10B8CV2)
11.3.2
This section describes in address order all the ADC10B8C registers and their individual bits.
11.3.2.1
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
380
Module Base + 0x0000
WRAP[3-0]
Reset
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
3-0
W
R
Reserved
Register Descriptions
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
multi-channel conversions. The coding is summarized in
ATD Control Register 0 (ATDCTL0)
0
7
WRAP3 WRAP2 WRAP1 WRAP0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
0
0
6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Table 11-2. Multi-Channel Wrap Around Coding
Figure 11-3. ATD Control Register 0 (ATDCTL0)
MC9S12G Family Reference Manual,
Table 11-1. ATDCTL0 Field Descriptions
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
5
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
4
Multiple Channel Conversions (MULT = 1)
Description
Wraparound to AN0 after Converting
WRAP3
Table
1
3
11-2.
Reserved
Rev.1.01
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN7
AN7
AN7
AN7
AN7
AN7
AN7
AN7
WRAP2
1
2
1
WRAP1
Freescale Semiconductor
1
1
WRAP0
1
0
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