MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 545

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

17.3.2.6
The PWMCTL register provides for various control of the PWM module.
Read: Anytime
Write: Anytime
There are up to four control bits for concatenation, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. If the corresponding channels do not exist on a particular derivative, then
writes to these bits have no effect and reads will return zeroes. When channels 6 and 7are concatenated,
channel 6 registers become the high order bytes of the double byte channel. When channels 4 and 5 are
concatenated, channel 4 registers become the high order bytes of the double byte channel. When channels
2 and 3 are concatenated, channel 2 registers become the high order bytes of the double byte channel.
When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double
byte channel.
See
Function.
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
Freescale Semiconductor
CON67
CON45
Reset
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Section 17.4.2.7, “PWM 16-Bit Functions”
Field
unavailable bits return a zero
7
6
W
R
CON67
Concatenate Channels 6 and 7
0 Channels 6 and 7 are separate 8-bit PWMs.
1 Channels 6 and 7 are concatenated to create one 16-bit PWM channel. Channel 6 becomes the high order
Concatenate Channels 4 and 5
0 Channels 4 and 5 are separate 8-bit PWMs.
1 Channels 4 and 5 are concatenated to create one 16-bit PWM channel. Channel 4 becomes the high order
PWM Control Register (PWMCTL)
0
7
Change these bits only when both corresponding channels are disabled.
byte and channel 7 becomes the low order byte. Channel 7 output pin is used as the output for this 16-bit
PWM (bit 7 of port PWMP). Channel 7 clock select control-bit determines the clock source, channel 7 polarity
bit determines the polarity, channel 7 enable bit enables the output and channel 7 center aligned enable bit
determines the output mode.
byte and channel 5 becomes the low order byte. Channel 5 output pin is used as the output for this 16-bit
PWM (bit 5 of port PWMP). Channel 5 clock select control-bit determines the clock source, channel 5 polarity
bit determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit
determines the output mode.
CON45
= Unimplemented or Reserved
0
6
Figure 17-8. PWM Control Register (PWMCTL)
Table 17-10. PWMCTL Field Descriptions
MC9S12G Family Reference Manual, Rev.1.01
CON23
5
0
for a more detailed description of the concatenation PWM
CON01
NOTE
0
4
Description
PSWAI
0
3
Pulse-Width Modulator (S12PWM8B8CV2)
PFRZ
2
0
0
0
1
0
0
0
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