MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 281

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.1.4
The DBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU monitoring is disabled. When
the CPU enters active BDM Mode through a BACKGROUND command, the DBG module, if already
armed, remains armed.
The DBG module tracing is disabled if the MCU is secure, however, breakpoints can still be generated
Freescale Semiconductor
Enable
BDM
•
•
•
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
x
0
0
1
1
— CPU breakpoint entering BDM on breakpoint (BDM)
— CPU breakpoint executing SWI on breakpoint (SWI)
Trigger mode independent of comparators
— TRIG Immediate software trigger
Four trace modes
— Normal: change of flow (COF) PC information is stored (see
— Loop1: same as Normal but inhibits consecutive duplicate source address entries
— Detail: address and data for all cycles except free cycles and opcode fetches are stored
— Compressed Pure PC: all program counter addresses are stored
4-stage state sequencer for trace buffer control
— Tracing session trigger linked to Final State of state sequencer
— Begin and End alignment of tracing to trigger
for change of flow definition.
Modes of Operation
Active
BDM
0
1
0
1
x
Secure
MCU
1
0
0
0
0
Table 8-1. Mode Dependent Restriction Summary
MC9S12G Family Reference Manual, Rev.1.01
Matches Enabled
Comparator
Yes
Yes
Yes
No
Active BDM not possible when not enabled
Breakpoints
Only SWI
Possible
Yes
Yes
No
Section 8.4.5.2.1, “Normal
Possible
Tagging
Yes
Yes
Yes
S12S Debug Module (S12SDBG)
No
Possible
Tracing
Yes
Yes
No
No
Mode)
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