MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 649

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

For the description of PACLK please refer
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an
input clock to the timer counter. The change from one selected clock to the other happens immediately
after these bits are written.
Freescale Semiconductor
CLK[1:0]
PEDGE
PAOVI
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
PAI
3:2
4
1
0
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1).
For PAMOD bit = 0 (event counter mode). See
0 Falling edges on IOC7 pin cause the count to be increased.
1 Rising edges on IOC7 pin cause the count to be increased.
For PAMOD bit = 1 (gated time accumulation mode).
0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling
1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge
Clock Select Bits — Refer to
Pulse Accumulator Overflow Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAOVF is set.
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAIF is set.
edge on IOC7 sets the PAIF flag.
on IOC7 sets the PAIF flag.
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
because the ÷64 clock is generated by the timer prescaler.
PAMOD
CLK1
0
0
1
1
0
0
1
1
Table 20-18. PACTL Field Descriptions (continued)
PEDGE
CLK0
MC9S12G Family Reference Manual, Rev.1.01
0
1
0
1
0
1
0
1
Table 20-20. Timer Clock Selection
Table
Table 20-19. Pin Action
Use PACLK/65536 as timer counter clock frequency
Use PACLK/256 as timer counter clock frequency
20-20.
Figure
Use timer prescaler clock as timer counter clock
Div. by 64 clock enabled with pin high level
Use PACLK as input to timer counter clock
Div. by 64 clock enabled with pin low level
NOTE
20-30.
Table
Description
20-19.
Timer Clock
Falling edge
Rising edge
Pin Action
Timer Module (TIM16B8CV3)
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