MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 287

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.3.2.4
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
8.3.2.5
Read: Only when unlocked AND unsecured AND not armed AND TSOURCE set.
Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer
contents.
Freescale Semiconductor
Address: 0x0024, 0x0025
Address: 0x0023
ABCM[1:0]
Resets
Reset
Other
Field
POR
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
1–0
1
W
W
R
R
Currently defaults to Comparator A, Comparator B disabled
ABCM
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
00
01
10
11
—
15
X
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
described in
Debug Control Register2 (DBGC2)
Debug Trace Buffer Register (DBGTBH:DBGTBL)
0
0
7
—
14
X
13
—
X
Table
Match0 mapped to comparator A match: Match1 mapped to comparator B match.
= Unimplemented or Reserved
0
0
6
8-9.
Figure 8-7. Debug Trace Buffer Register (DBGTB)
12
—
X
Match 0 mapped to comparator A/B outside range: Match1 disabled.
Figure 8-6. Debug Control Register2 (DBGC2)
Match 0 mapped to comparator A/B inside range: Match1 disabled.
MC9S12G Family Reference Manual, Rev.1.01
Table 8-8. DBGC2 Field Descriptions
11
—
X
5
0
0
Table 8-9. ABCM Encoding
—
10
X
—
X
9
0
0
4
Bit 8
—
Description
X
8
Description
Reserved
Bit 7
—
X
7
1
0
0
3
Bit 6
—
X
6
Bit 5
—
X
5
2
0
0
Bit 4
—
X
4
S12S Debug Module (S12SDBG)
Bit 3
—
X
3
0
1
Bit 2
—
X
2
ABCM
Bit 1
—
X
1
0
0
Bit 0
—
X
0
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