MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 363

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

10.4
10.4.1
The PLL is used to generate a high speed PLLCLK based on a low frequency REFCLK.
The REFCLK is by default the IRCCLK which is trimmed to f
If using the oscillator (OSCE=1) REFCLK will be based on OSCCLK. For increased flexibility, OSCCLK
can be divided in a range of 1 to 16 to generate the reference frequency REFCLK using the REFDIV[3:0]
bits. Based on the SYNDIV[5:0] bits the PLL generates the VCOCLK by multiplying the reference clock
by a 2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2,
3, 4, 5, 6,... to 32 to generate the PLLCLK.
Several examples of PLL divider settings are shown in
optimum stability and shortest lock time:
Freescale Semiconductor
.
If oscillator is enabled (OSCE=1)
f
If oscillator is disabled (OSCE=0)
f VCO
If PLL is selected (PLLSEL=1)
•
•
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
off
osc
Use lowest possible f
Use highest possible REFCLK frequency f
REFDIV[3:
Functional Description
=
Phase Locked Loop with Internal Filter (PLL)
2 f REF
$00
0]
×
Although it is possible to set the dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
1MHz
×
f
REF
(
SYNDIV
REFFRQ[1:0] SYNDIV[5:0]
VCO
Table 10-25. Examples of PLL Divider Settings
+
00
MC9S12G Family Reference Manual, Rev.1.01
/ f
f PLL
f bus
1
f PLL
)
REF
=
=
=
f REF
f REF
ratio (SYNDIV value).
f PLL
------------ -
---------------------------------------- -
(
f VCO
---------------
POSTDIV
2
4
$18
=
=
f VCO
------------------------------------
(
f IRC1M
REFDIV
NOTE
REF
f OSC
+
50MHz
.
1
f
VCO
Table
)
+
1
S12 Clock, Reset and Power Management Unit (S12CPMU)
)
VCOFRQ[1:0]
10-25. The following rules help to achieve
IRC1M_TRIM
01
POSTDIV
=1MHz.
[4:0]
$03
12.5MHz
f
PLL
6.25MHz
f
bus
363