MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 631

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 20
Timer Module (TIM16B8CV3)
20.1
The basic scalable timer consists of a 16-bit, software-programmable counter driven by a flexible
programmable prescaler.
This timer can be used for many purposes, including input waveform measurements while simultaneously
generating an output waveform. Pulse widths can vary from microseconds to many seconds.
This timer could contain up to 8 (0....7) input capture/output compare channels with one pulse accumulator
available only on channel 7. The input capture function is used to detect a selected transition edge and
record the time. The output compare function is used for generating output signals or for timer software
delays. The 16-bit pulse accumulator is used to operate as a simple event counter or a gated time
accumulator. The pulse accumulator shares timer channel 7 when the channel is available and when in
event mode.
A full access for the counter registers or the input capture/output compare registers should take place in
one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the
same result as accessing them in one word.
20.1.1
The TIM16B8CV3 includes these distinctive features:
Freescale Semiconductor
V03.00
V03.01
V03.02
•
•
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Up to 8 channels available. (refer to device specification for exact number)
All channels have same input capture/output compare functionality.
Introduction
Features
Aug. 26, 2009
Jan. 28, 2009
Apri,12,2010
20.3.2.2/20-638,
20.3.2.3/20-639,
20.3.2.4/20-639,
Figure 20-4./20-
20.3.2.15/20-64
20.3.2.8/20-642
20.3.2.11/20-64
20.1.2/20-632
20.4.3/20-655
20.4.3/20-655
635
MC9S12G Family Reference Manual, Rev.1.01
8
5
Initial version
- Correct typo: TSCR ->TSCR1;
- Correct typo: ECTxxx->TIMxxx
- Correct reference:
- Add description, “a counter overflow when TTOV[7] is set”, to be the
condition of channel 7 override event.
- Phrase the description of OC7M to make it more explicit
-Add
-update TCRE bit description
-add
Figure 20-31
Table 20-10
Table 20-1.
Figure 20-25
->
Figure 20-30
631