MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 547

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
The clock source of each PWM channel is determined by PCLKx bits in PWMCLK (see
“PWM Clock Select Register
and
17.3.2.8
PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is
generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two.
Freescale Semiconductor
PCLKAB7
PCLKAB6
PCLKAB5
PCLKAB4
PCLKAB3
PCLKAB2
PCLKAB1
PCLKAB0
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Field
Table
unavailable bits return a zero
7
6
5
4
3
2
1
0
Clock SA = Clock A / (2 * PWMSCLA)
17-6.
Pulse Width Channel 7 Clock A/B Select
0 Clock B or SB is the clock source for PWM channel 7, as shown in
1 Clock A or SA is the clock source for PWM channel 7, as shown in
Pulse Width Channel 6 Clock A/B Select
0 Clock B or SB is the clock source for PWM channel 6, as shown in
1 Clock A or SA is the clock source for PWM channel 6, as shown in
Pulse Width Channel 5 Clock A/B Select
0 Clock A or SA is the clock source for PWM channel 5, as shown in
1 Clock B or SB is the clock source for PWM channel 5, as shown in
Pulse Width Channel 4 Clock A/B Select
0 Clock A or SA is the clock source for PWM channel 4, as shown in
1 Clock B or SB is the clock source for PWM channel 4, as shown in
Pulse Width Channel 3 Clock A/B Select
0 Clock B or SB is the clock source for PWM channel 3, as shown in
1 Clock A or SA is the clock source for PWM channel 3, as shown in
Pulse Width Channel 2 Clock A/B Select
0 Clock B or SB is the clock source for PWM channel 2, as shown in
1 Clock A or SA is the clock source for PWM channel 2, as shown in
Pulse Width Channel 1 Clock A/B Select
0 Clock A or SA is the clock source for PWM channel 1, as shown in
1 Clock B or SB is the clock source for PWM channel 1, as shown in
Pulse Width Channel 0 Clock A/B Select
0 Clock A or SA is the clock source for PWM channel 0, as shown in
1 Clock B or SB is the clock source for PWM channel 0, as shown in
PWM Scale A Register (PWMSCLA)
Register bits PCLKAB0 to PCLKAB7 can be written anytime. If a clock
select is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
(PWMCLK)) and PCLKABx bits in PWMCLKAB as shown in
Table 17-11. PWMCLK Field Descriptions
MC9S12G Family Reference Manual, Rev.1.01
NOTE
Description
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Pulse-Width Modulator (S12PWM8B8CV2)
17-6.
17-6.
17-6.
17-6.
17-5.
17-5.
17-5.
17-5.
17-6.
17-6.
17-6.
17-6.
17-5.
17-5.
17-5.
17-5.
Section 17.3.2.3,
Table 17-5
547