MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 142

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Analog-to-Digital Converter (S08ADC12V1)
142
COCO
ADCO
ADCH
Field
AIEN
4:0
7
6
5
Reset:
W
R
Conversion Complete Flag. The COCO flag is a read-only bit set each time a conversion is completed when the
compare function is disabled (ACFE = 0). When the compare function is enabled (ACFE = 1), the COCO flag is
set upon completion of a conversion only if the compare result is true. This bit is cleared when ADCSC1 is written
or when ADCRL is read.
0 Conversion not completed
1 Conversion completed
Interrupt Enable AIEN enables conversion complete interrupts. When COCO becomes set while AIEN is high,
an interrupt is asserted.
0 Conversion complete interrupt disabled
1 Conversion complete interrupt enabled
Continuous Conversion Enable. ADCO enables continuous conversions.
0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one
1 Continuous conversions initiated following a write to ADCSC1 when software triggered operation is selected.
Input Channel Select. The ADCH bits form a 5-bit field that selects one of the input channels. The input channels
are detailed in
The successive approximation converter subsystem is turned off when the channel select bits are all set. This
feature allows for explicit disabling of the ADC and isolation of the input channel from all sources. Terminating
continuous conversions this way prevents an additional, single conversion from being performed. It is not
necessary to set the channel select bits to all ones to place the ADC in a low-power state when continuous
conversions are not enabled because the module automatically enters a low-power state when a conversion
completes.
conversion following assertion of ADHWT when hardware triggered operation is selected.
Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected.
COCO
7
0
Table
Figure 10-3. Status and Control Register (ADCSC1)
AIEN
0
6
10-4.
Table 10-3. ADCSC1 Field Descriptions
MC9S08JM60 Series Data Sheet, Rev. 3
00000–01111
10000–11011
Table 10-4. Input Channel Select
ADCO
ADCH
11100
11101
11110
11111
0
5
1
4
Description
Module disabled
Input Select
Reserved
AD16–27
AD0–15
V
V
REFH
REFL
1
3
ADCH
1
2
Freescale Semiconductor
1
1
1
0