MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 254

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Serial Peripheral Interface (S08SPI16V1)
15.3.5
The SPI data registers (SPIxDH:SPIxDL) are both the input and output register for SPI data. A write to
these registers writes to the transmit data buffer, allowing data to be queued and transmitted.
254
Reset
Reset
SPTEF
MODF
SPMF
SPRF
Field
7
6
5
4
W
W
R
R
Bit 15
SPI Data Registers (SPIxDH:SPIxDL)
Bit 7
SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may
be read from the SPI data register (SPIxDH:SPIxDL). SPRF is cleared by reading SPRF while it is set, then
reading the SPI data register.
0 No data available in the receive data buffer.
1 Data available in the receive data buffer.
SPI Match Flag — SPMF is set after SPRF = 1 when the value in the receive data buffer matches the value in
SPIMH:SPIML. To clear the flag, read SPMF when it is set, then write a 1 to it.
0 Value in the receive data buffer does not match the value in SPIxMH:SPIxML registers.
1 Value in the receive data buffer matches the value in SPIxMH:SPIxML registers.
SPI Transmit Buffer Empty Flag — This bit is set when the transmit data buffer is empty. It is cleared by reading
SPIxS with SPTEF set, followed by writing a data value to the transmit buffer at SPIxDH:SPIxDL. SPIxS must be
read with SPTEF = 1 before writing data to SPIxDH:SPIxDL or the SPIxDH:SPIxDL write will be ignored. SPTEF
is automatically set when all data from the transmit buffer transfers into the transmit shift register. For an idle SPI,
data written to SPIxDH:SPIxDL is transferred to the shifter almost immediately so SPTEF is set within two bus
cycles allowing a second data to be queued into the transmit buffer. After completion of the transfer of the data
in the shift register, the queued data from the transmit buffer will automatically move to the shifter and SPTEF will
be set to indicate there is room for new data in the transmit buffer. If no new data is waiting in the transmit buffer,
SPTEF simply remains set and no data moves from the buffer to the shifter.
0 SPI transmit buffer not empty
1 SPI transmit buffer empty
Master Mode Fault Flag — MODF is set if the SPI is configured as a master and the slave select input goes low,
indicating some other SPI device is also configured as a master. The SS pin acts as a mode fault error input only
when MSTR = 1, MODFEN = 1, and SSOE = 0; otherwise, MODF will never be set. MODF is cleared by reading
MODF while it is 1, then writing to SPI control register 1 (SPIxC1).
0 No mode fault error
1 Mode fault error detected
0
0
7
7
14
0
6
0
6
6
Table 15-8. SPIxS Register Field Descriptions
Figure 15-10. SPI Data Register Low (SPIxDL)
Figure 15-9. SPI Data Register High (SPIxDH)
MC9S08JM60 Series Data Sheet, Rev. 3
13
0
5
0
5
5
12
0
4
0
4
4
Description
11
3
0
3
3
0
10
0
2
0
2
2
Freescale Semiconductor
9
0
1
0
1
1
Bit 8
Bit 0
0
0
0
0