MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 75

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

1
2
must be written during the user’s reset initialization program to set the desired controls even if the desired
settings are the same as the reset settings.
Freescale Semiconductor
COPT[1:0]
Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column
displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode
(COPW = 1).
Values shown in milliseconds based on t
tolerance of this value.
Reset
STOPE
COPCLKS
Field
7:6
5
W
N/A
R
0
0
0
1
1
1
Control Bits
COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with
COPCLKS in SOPT2 defines the COP timeout period. See
Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
1
7
COPT
COPT[1:0]
= Unimplemented or Reserved
0:0
0:1
1:0
1:1
0:1
1:0
1:1
1
6
Figure 5-5. System Options Register (SOPT1)
Table 5-5. SOPT1 Register Field Descriptions
Clock Source
Table 5-6. COP Configuration Options
1 kHz LPO
1 kHz LPO
1 kHz LPO
MC9S08JM60 Series Data Sheet, Rev. 3
LPO
STOPE
BUSCLK
BUSCLK
BUSCLK
clock
clock
clock
0
N/A
5
= 1 ms. See t
COP Window
LPO
1
4
196,608 cycles
49,152 cycles
Description
(COPW = 1)
6144 cycles
in the appendix
N/A
N/A
N/A
N/A
1
Chapter 5 Resets, Interrupts, and System Configuration
Table
Opens
3
0
0
5-6.
Section A.12.1, “Control
0
0
2
COP Overflow Count
2
2
2
10
8
5
COP is disabled
cycles (256 ms
cycles (32 ms
cycles (1.024 s
2
2
2
13
16
18
cycles
cycles
cycles
1
1
Timing,” for the
2
1
1
)
)
)
1
0
75