MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 364

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

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5
6
7
Appendix A Electrical Characteristics
A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1
364
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via V
interval.
Jitter measurements are based upon a 48 MHz MCGOUT clock frequency..
Below D
is already in lock, then the MCG may stay in lock.
Below D
1
2
3
4
o
Num
Typical values are based on characterization data at V
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% V
1
2
3
4
5
6
7
8
9
lock
unl
C
minimum, the MCG will not exit lock if already in lock. Above D
minimum, the MCG is guaranteed to enter lock. Above D
Control Timing
Bus frequency (t
Internal low-power oscillator period
External reset pulse width
Reset low drive
Active background debug mode latch setup time
Active background debug mode latch hold time
IRQ pulse width
KBIPx pulse width
Port rise and fall time
low output drive (PTxDS = 0), (load = 50 pF)
high output drive (PTxDS = 1), (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control disabled (PTxSE = 0)
DD
Slew rate control enabled (PTxSE = 1)
Slew rate control enabled (PTxSE = 1)
and V
cyc
Parameter
SS
= 1/f
and variation in crystal oscillator frequency increase the C
Bus
DD
MC9S08JM60 Series Data Sheet, Rev. 3
2
)
Asynchronous path
Asynchronous path
and 80% V
Synchronous path
Synchronous path
Table A-13. Control Timing
DD
DD
levels. Temperature range –40 °C to 85 °C.
= 5.0 V, 25 °C unless otherwise stated.
4
2
3
2
3
t
t
t
lock
Symbol
Rise
ILIH,
ILIH,
t
t
t
MSSU
t
t
rstdrv
f
extrst
MSH
LPO
Bus
maximum, the MCG will not enter lock. But if the MCG
, t
t
t
unl
IHIL
IHIL
Fall
maximum, the MCG is guaranteed to exit lock.
1.5 x t
1.5 x t
66 x t
Min
800
100
500
100
100
100
dc
—
—
—
—
cyc
cyc
cyc
Typ
Jitter
40
75
11
35
—
—
—
1
Freescale Semiconductor
percentage for a given
1500
Max
24
—
—
—
—
—
—
BUS
.
MHz
Unit
μs
ns
ns
ns
ns
ns
ns
ns