MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 311

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

17.4
This section describes the functional behavior of the USB module. It documents data packet processing
for endpoint 0 and data endpoints, USB suspend and resume states, SOF token processing, reset conditions
and interrupts.
17.4.1
Figure 17-2
following sections. The module involves several major blocks — USB transceiver (XCVR), USB serial
interface engine (SIE), a 3.3 V regulator (VREG), endpoint buffer manager, shared RAM arbitration, USB
RAM and the SkyBlue gasket.
17.4.1.1
The SIE is composed of two major functions: TX Logic and RX Logic. These major functions are
described below in more detail. The TX and RX logic are connected by a USB protocol engine which
manages packet flow to and from the USB module. The SIE is connected to the rest of the system via
Freescale Semiconductor
EPCTLDIS
EPSTALL
EPHSHK
Field
X
X
X
1
0
4
0
1
Functional Description
Block Descriptions
is the block diagram. The module’s sub-blocks and external signals are described in the
USB Serial Interface Engine (SIE)
Endpoint Stall — When set, this bit indicates that the endpoint is stalled. This bit has priority over all other
control bits in the endpoint control register, but is only valid if EPTXEN=1 or EPRXEN=1. Any access to this
endpoint will cause the USB module to return a STALL handshake. Once an endpoint is stalled it requires
intervention from the host controller.
0 Endpoint n is not stalled
1 Endpoint n is stalled
Endpoint Handshake — This bit determines if the endpoint will perform handshaking during a transaction
to the endpoint. This bit will generally be set unless the endpoint is isochronous.
0 No handshaking performed during a transaction to this endpoint (usually for isochronous endpoints)
1 Handshaking performed during a transaction to this endpoint
Bit Name
EPRXEN
3
0
0
1
1
1
Table 17-18. EPCTLn Field Descriptions (continued)
Table 17-19. Endpoint Enable/Direction Control
EPTXEN
2
0
1
0
1
1
MC9S08JM60 Series Data Sheet, Rev. 3
Disable endpoint
Enable endpoint for IN(TX) transfers only
Enable endpoint for OUT(RX) transfers only
Enable endpoint for IN, OUT and SETUP transfers.
RESERVED
Description
Endpoint Enable/Direction Control
Universal Serial Bus Device Controller (S08USBV1)
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