MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 143

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

10.3.2
The ADCSC2 register controls the compare function, conversion trigger, and conversion active of the
ADC module.
10.3.3
In 12-bit operation, ADCRH contains the upper four bits of the result of a 12-bit conversion. In 10-bit
mode, ADCRH contains the upper two bits of the result of a 10-bit conversion. When configured for 10-bit
mode, ADR[11:10] are cleared. When configured for 8-bit mode, ADR[11:8] are cleared.
In 12-bit and 10-bit mode, ADCRH is updated each time a conversion completes except when automatic
compare is enabled and the compare condition is not met. When a compare event does occur, the value is
the addition of the conversion result and the two’s complement of the compare value. In 12-bit and 10-bit
mode, reading ADCRH prevents the ADC from transferring subsequent conversion results into the result
registers until ADCRL is read. If ADCRL is not read until after the next conversion is completed, the
intermediate conversion result is lost. In 8-bit mode, there is no interlocking with ADCRL.
Freescale Semiconductor
ADTRG
ADACT
ACFGT
ACFE
Field
1
7
6
5
4
Bits 1 and 0 are reserved bits that must always be written to 0.
Reset:
W
R
Status and Control Register 2 (ADCSC2)
Data Result High Register (ADCRH)
Conversion Active. Indicates that a conversion is in progress. ADACT is set when a conversion is initiated and
cleared when a conversion is completed or aborted.
0 Conversion not in progress
1 Conversion in progress
Conversion Trigger Select. Selects the type of trigger used for initiating a conversion. Two types of triggers are
selectable: software trigger and hardware trigger. When software trigger is selected, a conversion is initiated
following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated following the assertion
of the ADHWT input.
0 Software trigger selected
1 Hardware trigger selected
Compare Function Enable. Enables the compare function.
0 Compare function disabled
1 Compare function enabled
Compare Function Greater Than Enable. Configures the compare function to trigger when the result of the
conversion of the input being monitored is greater than or equal to the compare value. The compare function
defaults to triggering when the result of the compare of the input being monitored is less than the compare value.
0 Compare triggers when input is less than compare value
1 Compare triggers when input is greater than or equal to compare value
ADACT
7
0
ADTRG
Figure 10-4. Status and Control Register 2 (ADCSC2)
Table 10-5. ADCSC2 Register Field Descriptions
0
6
MC9S08JM60 Series Data Sheet, Rev. 3
ACFE
0
5
ACFGT
0
4
Description
0
0
3
Analog-to-Digital Converter (S08ADC12V1)
0
0
2
R
0
1
1
R
0
0
1
143