MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 3

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

MC9S08JM60 Series Features
8-Bit HCS08 Central Processor Unit (CPU)
Memory Options
Clock Source Options
System Protection
Power-Saving Modes
Peripherals
• 48-MHz HCS08 CPU (central processor unit)
• 24-MHz internal bus frequency
• HC08 instruction set with added BGND instruction
• Background debugging system
• Breakpoint capability to allow single breakpoint
• In-circuit emulator (ICE) debug module containing
• Support for up to 32 interrupt/reset sources
• Up to 60 KB of on-chip in-circuit programmable
• Up to 4 KB of on-chip RAM
• 256 bytes of USB RAM
• Clock source options include crystal, resonator,
• MCG (multi-purpose clock generator) — PLL and
• Optional computer operating properly (COP) reset
• Low-voltage detection with reset or interrupt
• Illegal opcode detection with reset
• Illegal address detection with reset
• Wait plus two stops
• USB — USB 2.0 full-speed (12 Mbps) device
• ADC — 12-channel, 12-bit analog-to-digital
• ACMP — Analog comparator with option to
• SCI — Two serial communications interface
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
two comparators and nine trigger modes. Eight
deep FIFO for storing change-of-flow addresses
and event-only data. Debug module supports both
tag and force breakpoints.
flash memory with block protection and security
options
external clock
FLL; internal reference clock with trim adjustment
with option to run from independent 1-kHz internal
clock source or the bus clock
controller with dedicated on-chip USB transceiver,
3.3-V regulator and USBDP pull-up resister;
supports control, interrupt, isochronous, and bulk
transfers; supports endpoint 0 and up to 6
additional endpoints; endpoints 5 and 6 can be
combined to provide double buffering capability
converter with automatic compare function;
internal temperature sensor
compare to internal reference; operation in stop3
mode
modules with optional 13-bit break LIN extensions
Input/Output
Package Options
• SPI — Two 8- or 16-bit selectable serial peripheral
• IIC — Inter-integrated circuit bus module to
• Timers — One 2-channel and one 6-channel
• KBI — 8-pin keyboard interrupt module
• RTC — Real-time counter with binary- or
• Up to 51 general-purpose input/output pins
• Software selectable pullups on ports when used
• Software selectable slew rate control on ports
• Software selectable drive strength on ports when
• Master reset pin and power-on reset (POR)
• Internal pullup on RESET, IRQ, and BKGD/MS
• 64-pin quad flat package (QFP)
• 64-pin low-profile quad flat package (LQFP)
• 48-pin quad flat no-lead (QFN)
• 44-pin low-profile quad flat package (LQFP)
interface modules with a receive data buffer
hardware match function
operate at up to 100 kbps with maximum bus
loading; multi-master operation; programmable
slave address; interrupt-driven byte-by-byte data
transfer; 10-bit addressing and broadcast modes
support
16-bit timer/pulse-width modulator (TPM)
modules: Selectable input capture, output
compare, and edge-aligned PWM capability on
each channel. Each timer module may be
configured for buffered, centered PWM (CPWM)
on all channels
decimal-based prescaler
as inputs
when used as outputs
used as outputs
pins to reduce customer system cost