MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 264

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Serial Peripheral Interface (S08SPI16V1)
In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by
the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case
the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur
in slave mode.
If a mode fault error occurs the SPI is switched to slave mode, with the exception that the slave output
buffer is disabled. So SPSCK, MISO and MOSI pins are forced to be high impedance inputs to avoid any
possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is
forced into idle state.
If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output
enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in
the bidirectional mode for the SPI system configured in slave mode.
The mode fault flag is cleared automatically by a read of the SPI Status Register (with MODF set) followed
by a write to SPI Control Register 1. If the mode fault flag is cleared, the SPI becomes a normal master or
slave again.
15.4.9
15.4.9.1
In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a
low-power, disabled state. SPI registers can still be accessed, but clocks to the core of this module are
disabled.
15.4.9.2
SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI Control Register 2.
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If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode
If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation
state when the CPU is in wait mode.
— If SPISWAI is set and the SPI is configured for master, any transmission and reception in
– If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in
progress stops at wait mode entry. The transmission and reception resumes when the SPI exits
wait mode.
progress continues if the SPSCK continues to be driven from the master. This keeps the slave
synchronized to the master and the SPSCK.
If the master transmits data while the slave is in wait mode, the slave will continue to send out
data consistent with the operation mode at the start of wait mode (i.e., if the slave is currently
sending its SPIxDH:SPIxDL to the master, it will continue to send the same byte. Otherwise,
if the slave is currently sending the last data received byte from the master, it will continue to
send each previously receive data from the master byte).
Low Power Mode Options
SPI in Run Mode
SPI in Wait Mode
MC9S08JM60 Series Data Sheet, Rev. 3
Freescale Semiconductor