MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 168

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

11.3.3
11.3.4
168
Reset
Reset
IICEN
TXAK
RSTA
Field
IICIE
MST
TX
7
6
5
4
3
2
W
W
R
R
IICEN
IIC Control Register (IICC1)
IIC Status Register (IICS)
TCF
IIC Enable. The IICEN bit determines whether the IIC module is enabled.
0 IIC is not enabled
1 IIC is enabled
IIC Interrupt Enable. The IICIE bit determines whether an IIC interrupt is requested.
0 IIC interrupt request not enabled
1 IIC interrupt request enabled
Master Mode Select. The MST bit changes from a 0 to a 1 when a start signal is generated on the bus and
master mode is selected. When this bit changes from a 1 to a 0 a stop signal is generated and the mode of
operation changes from master to slave.
0 Slave mode
1 Master mode
Transmit Mode Select. The TX bit selects the direction of master and slave transfers. In master mode, this bit
should be set according to the type of transfer required. Therefore, for address cycles, this bit is always high.
When addressed as a slave, this bit should be set by software according to the SRW bit in the status register.
0 Receive
1 Transmit
Transmit Acknowledge Enable. This bit specifies the value driven onto the SDA during data acknowledge
cycles for master and slave receivers.
0 An acknowledge signal is sent out to the bus after receiving one data byte
1 No acknowledge signal response is sent
Repeat start. Writing a 1 to this bit generates a repeated start condition provided it is the current master. This
bit is always read as cleared. Attempting a repeat at the wrong time results in loss of arbitration.
0
1
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
IICIE
IAAS
0
0
6
6
Figure 11-5. IIC Control Register (IICC1)
Figure 11-6. IIC Status Register (IICS)
Table 11-5. IICC1 Field Descriptions
MC9S08JM60 Series Data Sheet, Rev. 3
BUSY
MST
0
0
5
5
ARBL
TX
0
0
4
4
Description
TXAK
3
0
3
0
0
RSTA
SRW
0
0
0
2
2
Freescale Semiconductor
IICIF
0
0
0
1
1
RXAK
0
0
0
0
0