MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 159

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

There are some situations where external system activity causes radiated or conducted noise emissions or
excessive V
wait or stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise
on the accuracy:
10.6.2.4
The ADC quantizes the ideal straight-line transfer function into 4096 steps (in 12-bit mode). Each step
ideally has the same height (1 code) and width. The width is defined as the delta between the transition
points to one code and the next. The ideal code width for an N bit converter (in this case N can be 8, 10 or
12), defined as 1
There is an inherent quantization error due to the digitization of the result. For 8-bit or 10-bit conversions
the code transitions when the voltage is at the midpoint between the points where the straight line transfer
function is exactly represented by the actual transfer function. Therefore, the quantization error will be ±
1/2 lsb in 8- or 10-bit mode. As a consequence, however, the code width of the first (0x000) conversion is
only 1/2 lsb and the code width of the last (0xFF or 0x3FF) is 1.5 lsb.
For 12-bit conversions the code transitions only after the full code width is present, so the quantization
error is −1 lsb to 0 lsb and the code width of each step is 1 lsb.
10.6.2.5
The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these
errors but the system should be aware of them because they affect overall accuracy. These errors are:
Freescale Semiconductor
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— For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces V
There is no I/O switching, input or output, on the MCU during the conversion.
Place a 0.01 μF capacitor (C
noise issues, but affects the sample rate based on the external analog source resistance).
Average the result by converting the analog input many times in succession and dividing the sum
of the results. Four samples are required to eliminate the effect of a 1
Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and
averaging. Noise that is synchronous to ADCK cannot be averaged out.
Zero-scale error (E
the actual code width of the first conversion and the ideal code width (1/2 lsb in 8-bit or 10-bit
modes and 1 lsb in 12-bit mode). If the first conversion is 0x001, the difference between the actual
0x001 code width and its ideal (1 lsb) is used.
Full-scale error (E
the last conversion and the ideal code width (1.5 lsb in 8-bit or 10-bit modes and 1
mode). If the last conversion is 0x3FE, the difference between the actual 0x3FE code width and its
ideal (1
noise but increases effective conversion time due to stop recovery.
DD
Code Width and Quantization Error
Linearity Errors
LSB
noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in
LSB
) is used.
, is:
FS
ZS
) — This error is defined as the difference between the actual code width of
) (sometimes called offset) — This error is defined as the difference between
1 lsb = (V
MC9S08JM60 Series Data Sheet, Rev. 3
AS
) on the selected input channel to V
REFH
- V
REFL
) / 2
N
Analog-to-Digital Converter (S08ADC12V1)
REFL
LSB
or V
, one-time error.
SSAD
(this improves
LSB
in 12-bit
Eqn. 10-2
DD
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