MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 252

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Serial Peripheral Interface (S08SPI16V1)
15.3.3
This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
252
SPPR[2:0]
SPR[2:0]
Reset
Field
6:4
2:0
W
R
SPI Baud Rate Register (SPIxBR)
SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler
as shown in
drives the input of the SPI baud rate divider (see
for details.
SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in
Table
Section 15.4.6, “SPI Baud Rate
0
0
7
Bidirectional
Bidirectional
Pin Mode
Normal
Normal
15-7. The input to this divider comes from the SPI baud rate prescaler (see
= Unimplemented or Reserved
Table
SPPR2
0
6
15-6. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler
Table 15-5. SPIxBR Register Field Descriptions
SPC0
Figure 15-7. SPI Baud Rate Register (SPIxBR)
Table 15-4. Bidirectional Pin Configurations
0
1
0
1
MC9S08JM60 Series Data Sheet, Rev. 3
SPPR1
0
5
BIDIROE
Generation,” for details.
Master Mode of Operation
Slave Mode of Operation
X
X
0
1
0
1
SPPR0
MISO not used by SPI
0
4
Figure
Description
Slave Out
Master In
Slave I/O
Slave In
MISO
15-15). See
3
0
0
Section 15.4.6, “SPI Baud Rate
MOSI not used by SPI
SPR2
0
2
Master Out
Master I/O
Master In
Slave In
MOSI
Figure
Freescale Semiconductor
SPR1
15-15). See
0
1
Generation,”
SPR0
0
0