MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 200

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Multi-Purpose Clock Generator (S08MCGV1)
The table below shows MCGOUT frequency calculations using RDIV, BDIV, and VDIV settings for each
clock mode. The bus frequency is equal to MCGOUT divided by 2.
This section will include 3 mode switching examples using a 4 MHz external crystal. If using an external
clock source less than 1 MHz, the MCG should not be configured for any of the PLL modes (PEE and
PBE).
12.5.2.1
In this example, the MCG will move through the proper operational modes from FEI to PEE mode until
the 4 MHz crystal reference frequency is set to achieve a bus frequency of 8 MHz. Because the MCG is in
FEI mode out of reset, this example also shows how to initialize the MCG for PEE mode out of reset. First,
the code sequence will be described. Then a flowchart will be included which illustrates the sequence.
200
1. First, FEI must transition to FBE mode:
1
FEI (FLL engaged internal)
FEE (FLL engaged external)
FBE (FLL bypassed external)
FBI (FLL bypassed internal)
PEE (PLL engaged external)
PBE (PLL bypassed external)
BLPI (Bypassed low power internal)
BLPE (Bypassed low power external)
a) MCGC2 = 0x36 (%00110110)
b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit
R is the reference divider selected by the RDIV bits, B is the bus frequency divider selected by the BDIV bits,
and M is the multiplier selected by the VDIV bits.
– BDIV (bits 7 and 6) set to %00, or divide-by-1
– RANGE (bit 5) set to 1 because the frequency of 4 MHz is within the high frequency range
– HGO (bit 4) set to 1 to configure external oscillator for high gain operation
– EREFS (bit 2) set to 1, because a crystal is being used
– ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active
has been initialized.
Example # 1: Moving from FEI to PEE Mode: External Crystal = 4 MHz,
Bus Frequency = 8 MHz
Clock Mode
Table 12-6. MCGOUT Frequency Calculation Options
MC9S08JM60 Series Data Sheet, Rev. 3
(f
(f
f
f
[(f
f
f
f
ext
int
ext
int
ext
int
ext
ext
/ B
/ B
/ B
/ B
/ B
* 1024) / B
/ R *1024) / B
/ R) * M] / B
f
MCGOUT
1
Typical f
immediately after reset. RDIV
bits set to %000.
f
31.25 kHz to 39.0625 kHz
f
31.25 kHz to 39.0625 kHz
Typical f
f
MHz to 2 MHz
f
MHz to 2 MHz
ext
ext
ext
ext
/ R must be in the range of
/ R must be in the range of
/ R must be in the range of 1
/ R must be in the range of 1
MCGOUT
int
= 32 kHz
Note
Freescale Semiconductor
= 16 MHz