MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 71

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

5.6
The MC9S08JM60 series includes a system to protect against low-voltage conditions in order to protect
memory contents and control MCU system states during supply voltage variations. The system is
comprised of a power-on reset (POR) circuit and a LVD circuit with trip voltages for warning and
detection. The LVD circuit is enabled when LVDE in SPMSC1 is set to 1. The LVD is disabled upon
entering any of the stop modes unless LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then
the MCU cannot enter stop2 (it will enter stop3 instead), and the current consumption in stop3 with the
LVD enabled will be higher.
5.6.1
When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset
rearm voltage level, V
LVD circuit will hold the MCU in reset until the supply has risen above the low voltage detection low
threshold, V
5.6.2
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. The low voltage detection threshold is determined by the LVDV bit. After an LVD reset has
occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the low
voltage detection threshold. The LVD bit in the SRS register is set following either an LVD reset or POR.
5.6.3
The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is
approaching the low voltage condition. When a low voltage warning condition is detected and is
configured for interrupt operation (LVWIE set to 1), LVWF in SPMSC1 will be set and an LVW interrupt
request will occur.
Freescale Semiconductor
Number
Vector
1
0
Low-Voltage Detect (LVD) System
Power-On Reset Operation
Low-Voltage Detection (LVD) Reset Operation
Low-Voltage Warning (LVW) Interrupt Operation
LVDL
0xFFFC:FFFD
0xFFFE:FFFF
(High/Low)
Address
Table 5-1. Vector Summary (from Lowest to Highest Priority) (continued)
. Both the POR bit and the LVD bit in SRS are set following a POR.
POR
, the POR circuit will cause a reset condition. As the supply voltage rises, the
Vector Name
Vreset
Vswi
MC9S08JM60 Series Data Sheet, Rev. 3
Module
System
control
Core
SWI Instruction
Illegal opcode
RESET pin
Source
BDFR
COP
POR
LOC
LVD
Chapter 5 Resets, Interrupts, and System Configuration
Enable
LVDRE
COPE
BDFR
ILOP
CME
POR
—
—
Low-voltage detect
Software interrupt
BDM-forced reset
Watchdog timer
Power-on-reset
Illegal opcode
Loss of clock
Description
External pin
71