MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 74
MC9S08JM60CLH
Manufacturer Part Number
MC9S08JM60CLH
Description
Manufacturer
Freescale
Datasheet
1.MC9S08JM60CLH.pdf
(388 pages)
Specifications of MC9S08JM60CLH
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
24MHz
Interface Type
SCI/SPI
Total Internal Ram Size
4KB
# I/os (max)
51
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
12-chx12-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
60KB
Lead Free Status / RoHS Status
Compliant
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Chapter 5 Resets, Interrupts, and System Configuration
5.7.3
This register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
5.7.4
This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a
write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT
(intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT
74
BDFR is writable only through serial background debug commands, not from user programs.
Reset
BDFR
Field
Field
ILOP
COP
LOC
LVD
5
4
2
1
0
W
R
System Background Debug Force Reset Register (SBDFR)
System Options Register 1 (SOPT1)
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source may be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
Loss-of-Clock Reset — Reset was caused by a loss of external clock.
0 Reset not caused by a loss of external clock.
1 Reset caused by a loss of external clock.
Low Voltage Detect — If the LVD is enable with the LVDRE or LVDSE bit is set, and the supply drops below the
LVD trip voltage, an LVD reset will occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
Background Debug Force Reset — A serial background command such as WRITE_BYTE may be used to
allow an external debug host to force a target system reset. Writing logic 1 to this bit forces an MCU reset. This
bit cannot be written from a user program.
0
0
7
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
= Unimplemented or Reserved
Table 5-3. SRS Register Field Descriptions (continued)
0
0
6
Table 5-4. SBDFR Register Field Descriptions
MC9S08JM60 Series Data Sheet, Rev. 3
0
0
5
0
0
4
Description
Description
3
0
0
0
0
2
Freescale Semiconductor
0
0
1
BDFR
0
0
0
1
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