MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 262

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Serial Peripheral Interface (S08SPI16V1)
The baud rate divisor equation is as follows:
The baud rate can be calculated with the following equation:
15.4.7
15.4.7.1
The SS output feature automatically drives the SS pin low during transmission to select external devices
and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin
is connected to the SS input pin of the external device.
The SS output is available only in master mode during normal SPI operation by asserting the SSOE and
MODFEN bits as shown in
The mode fault feature is disabled while SS output is enabled.
15.4.7.2
The bidirectional mode is selected when the SPC0 bit is set in SPI Control Register 2 (see
this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit
decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and
the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and
MOSI pin in slave mode are not used by the SPI.
262
Special Features
SS Output
Bidirectional Mode (MOMI or SISO)
Care must be taken when using the SS output feature in a multi-master
system since the mode fault feature is not available for detecting system
errors between masters.
BUS CLOCK
Table
SPPR2:SPPR1:SPPR0
Figure 15-15. SPI Baud Rate Generation
1, 2, 3, 4, 5, 6, 7, or 8
Baud Rate
BaudRateDivisor
15-2.
MC9S08JM60 Series Data Sheet, Rev. 3
PRESCALER
DIVIDE BY
=
BusClock BaudRateDivisor
NOTE
=
(
⁄
SPPR
2, 4, 8, 16, 32, 64, 128, or 256
+
BAUD RATE DIVIDER
SPR2:SPR1:SPR0
1
) 2
DIVIDE BY
•
(
SPR
+
1
)
Freescale Semiconductor
MASTER
SPI
BIT RATE
Table
15-9.) In