MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 281

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

16.3.2
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where
they remain latched until the other half is read. This allows coherent 16-bit reads in either big-endian or
little-endian order which makes this more friendly to various compiler implementations. The coherency
mechanism is automatically restarted by an MCU reset or any write to the timer status/control register
(TPMxSC).
Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the
TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data
involved in the write.
Freescale Semiconductor
CLKS[B:A]
PS[2:0]
Field
4–3
2–0
Clock source selects. As shown in
three clock sources to drive the counter prescaler. The fixed system clock source is only meaningful in systems
with a PLL-based system clock. When there is no PLL, the fixed-system clock source is the same as the bus rate
clock. The external source is synchronized to the bus clock by TPM module, and the fixed system clock source
(when a PLL is present) is synchronized to the bus clock by an on-chip synchronization circuit. When a PLL is
present but not enabled, the fixed-system clock source is the same as the bus-rate clock.
Prescale factor select. This 3-bit field selects one of 8 division factors for the TPM clock input as shown in
Table
the clock source selected to drive the TPM system. The new prescale factor will affect the clock source on the
next system clock cycle after the new value is updated into the register bits.
TPM-Counter Registers (TPMxCNTH:TPMxCNTL)
16-4. This prescaler is located after any clock source synchronization or clock source selection so it affects
CLKSB:CLKSA
Table 16-2. TPMxSC Field Descriptions (continued)
PS2:PS1:PS0
000
001
010
011
100
101
110
111
Table 16-3. TPM-Clock-Source Selection
00
01
10
11
Table 16-4. Prescale Factor Selection
MC9S08JM60 Series Data Sheet, Rev. 3
Table
No clock selected (TPM counter disable)
TPM Clock Source to Prescaler Input
16-3, this 2-bit field is used to disable the TPM system or select one of
TPM Clock Source Divided-by
Fixed system clock
Description
External source
Bus rate clock
128
16
32
64
1
2
4
8
Timer/PWM Module (S08TPMV3)
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