MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 17

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

17.3 Register Definition ........................................................................................................................300
17.4 Functional Description ..................................................................................................................311
18.1 Introduction ...................................................................................................................................327
18.2 Background Debug Controller (BDC) ..........................................................................................328
18.3 On-Chip Debug System (DBG) ....................................................................................................337
18.4 Register Definition ........................................................................................................................341
Freescale Semiconductor
17.2.3 V
17.3.1 USB Control Register 0 (USBCTL0) .............................................................................301
17.3.2 Peripheral ID Register (PERID) .....................................................................................301
17.3.3 Peripheral ID Complement Register (IDCOMP) ............................................................302
17.3.4 Peripheral Revision Register (REV) ...............................................................................302
17.3.5 Interrupt Status Register (INTSTAT) ..............................................................................303
17.3.6 Interrupt Enable Register (INTENB) ..............................................................................304
17.3.7 Error Interrupt Status Register (ERRSTAT) ...................................................................305
17.3.8 Error Interrupt Enable Register (ERRENB) ...................................................................306
17.3.9 Status Register (STAT) ....................................................................................................307
17.3.10Control Register (CTL) ...................................................................................................308
17.3.11Address Register (ADDR) ..............................................................................................309
17.3.12Frame Number Register (FRMNUML, FRMNUMH) ...................................................309
17.3.13Endpoint Control Register (EPCTLn, n=0-6) .................................................................310
17.4.1 Block Descriptions ..........................................................................................................311
17.4.2 Buffer Descriptor Table (BDT) .......................................................................................316
17.4.3 USB Transactions ...........................................................................................................319
17.4.4 USB Packet Processing ...................................................................................................321
17.4.5 Start of Frame Processing ...............................................................................................322
17.4.6 Suspend/Resume .............................................................................................................323
17.4.7 Resets ..............................................................................................................................324
17.4.8 Interrupts .........................................................................................................................325
18.1.1 Features ...........................................................................................................................328
18.2.1 BKGD Pin Description ...................................................................................................329
18.2.2 Communication Details ..................................................................................................330
18.2.3 BDC Commands .............................................................................................................334
18.2.4 BDC Hardware Breakpoint .............................................................................................336
18.3.1 Comparators A and B .....................................................................................................337
18.3.2 Bus Capture Information and FIFO Operation ...............................................................337
18.3.3 Change-of-Flow Information ..........................................................................................338
18.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................338
18.3.5 Trigger Modes .................................................................................................................339
18.3.6 Hardware Breakpoints ....................................................................................................341
18.4.1 BDC Registers and Control Bits .....................................................................................341
18.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................343
18.4.3 DBG Registers and Control Bits .....................................................................................344
USB33 ............................................................................................................................................................. 300
MC9S08JM60 Series Data Sheet, Rev. 3
Development Support
Chapter 18
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