MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 324

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Universal Serial Bus Device Controller (S08USBV1)
17.4.6.2.2
Reset can wake a device from the suspend state.
17.4.6.2.3
The USB device can send a resume event to the host by writing to the CRESUME bit. Firmware must first
set the bit for the time period required by the USB Specification Rev. 2.0 (Section 7.1.7.7) and then clear
it to 0.
17.4.7
The module supports multiple types of resets. The first is a bus reset generated by the USB Host, the
second is a module reset generated by the MCU.
17.4.7.1
At any time, the USB host may issue a reset to one or all of the devices attached to the bus. A USB reset
is defined as a period of single ended zero (SE0) on the cable for greater than 2.5 μs. When the device
detects reset signaling, it resets itself to the unconfigured state, and sets its USB address zero. The USB
host uses reset signaling to force one or all connected devices into a known state prior to commencing
enumeration.
The USB module responds to reset signaling by asserting the USBRST interrupt in the INTSTAT register.
Software is required to service this interrupt to ensure correct operation of the USB.
17.4.7.2
USB module resets are initiated on-chip. During a module reset, the USB module is configured in the
default mode. The USB module can also be forced into its reset state by setting the USBRESET bit in the
USBCTL0 register. The default mode includes the following settings:
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a resume from low-power suspend. This will trigger an asynchronous interrupt to wake the CPU
from stop3 mode and resume clocks to the USB module.
Interrupts masked.
USB clock enabled
USB voltage regulator disabled
Resets
USB Bus Reset
USB Module Reset
As a precaution, after LPRESF is set, firmware must check the state of the
USB bus to see if the K-state was a result of a transient event and not a true
host-initiated resume. If this is the case, then the device can drop back into
stop3 if necessary. To do this, the RESUME interrupt can be enabled in
conjunction with the USBRESMEN feature. Then, after LPRESF is set, and
a K-state is still detected approximately 2.5 µs after clocks have restarted,
firmware can check that the RESUMEF interrupt has triggered, indicating
resume signaling from the host.
USB Reset Signaling
Remote Wakeup
MC9S08JM60 Series Data Sheet, Rev. 3
NOTE
Freescale Semiconductor