MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 307

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

17.3.9
The STAT reports the transaction status within the USB module. When the MCU receives a TOKDNE
interrupt, the STAT is read to determine the status of the previous endpoint communication. The data in
the status register is valid only when the TOKDNEF interrupt flag is asserted. The STAT register is actually
a read window into a status FIFO maintained by the USB module. When the USB module uses a BD, it
updates the status register. If another USB transaction is performed before the TOKDNE interrupt is
serviced, the USB module will store the status of the next transaction in the STAT FIFO. Thus, the STAT
register is actually a four byte FIFO which allows the microcontroller to process one transaction while the
serial interface engine (SIE) is processing the next. Clearing the TOKDNEF bit in the INTSTAT register
causes the SIE to update the STAT register with the contents of the next STAT value. If the next data in the
STAT FIFO holding register is valid, the SIE will immediately reassert the TOKDNE interrupt.
Freescale Semiconductor
ENDP[3:0]
PIDERR
Reset
CRC5
Field
Field
7–4
1
0
W
R
Status Register (STAT)
CRC5 Interrupt Enable — Setting this bit will enable CRC5 interrupts.
0 Interrupt disabled
1 Interrupt enabled
PIDERR Interrupt Enable — Setting this bit will enable PIDERR interrupts.
0 Interrupt disabled
1 Interrupt enabled
Endpoint Number — These four bits encode the endpoint address that received or transmitted the previous
token. This allows the microcontroller to determine which BDT entry was updated by the last USB transaction.
0000 Endpoint 0
0001 Endpoint 1
0010 Endpoint 2
0011 Endpoint 3
0100 Endpoint 4
0101 Endpoint 5
0110 Endpoint 6
0
7
= Unimplemented or Reserved
0
6
Table 17-12. ERRSTAT Field Descriptions (continued)
ENDP[3:0]
Table 17-13. STAT Field Descriptions
Figure 17-12. Status Register (STAT)
MC9S08JM60 Series Data Sheet, Rev. 3
0
5
0
4
Description
Description
IN
3
0
Universal Serial Bus Device Controller (S08USBV1)
ODD
0
2
0
0
1
0
0
0
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