MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 77

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

1
2
5.7.7
This high page register contains status and control bits to support the low-voltage detect function, and to
enable the bandgap voltage reference for use by the ADC module. This register must be written during the
user’s reset initialization program to set the desired controls even if the desired settings are the same as the
reset settings.
Freescale Semiconductor
LVWF will be set in the case when V
This bit can be written only one time after reset. Additional writes are ignored.
Reserved
Reset:
Reset
ID[11:8]
ID[7:0]
Field
Field
7:4
3:0
7:0
W
W
R
R
LVWF
System Power Management Status and Control 1 Register
(SPMSC1)
Bits 7:4 are reserved. Reading these bits will result in an indeterminate value; writes have no effect.
Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The
MC9S08JM60 Series is hard coded to the value 0x016. See also ID bits in
ID7
Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The
MC9S08JM60 Series is hard coded to the value 0x016. See also ID bits in
Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1)
0
0
7
7
1
= Unimplemented or Reserved
Figure 5-8. System Device Identification Register — Low (SDIDL)
= Unimplemented or Reserved
LVWACK
ID6
0
0
0
6
6
Table 5-8. SDIDH Register Field Descriptions
Table 5-9. SDIDL Register Field Descriptions
Supply
MC9S08JM60 Series Data Sheet, Rev. 3
LVWIE
ID5
transitions below the trip point or after reset and V
0
0
5
5
LVDRE
ID4
1
1
4
4
2
Description
Description
LVDSE
Chapter 5 Resets, Interrupts, and System Configuration
ID3
3
0
3
1
LVDE
ID2
Table
1
Table
1
2
2
2
Supply
5-9.
5-8.
is already below V
ID1
1
0
0
1
1
BGBE
ID0
LVW
0
0
0
0
.
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