MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 194

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Multi-Purpose Clock Generator (S08MCGV1)
In FLL bypassed external mode, the MCGOUT clock is derived from the external reference clock. The
external reference clock which is enabled can be an external crystal/resonator or it can be another external
clock source.The FLL clock is controlled by the external reference clock, and the FLL clock frequency
locks to 1024 times the reference frequency, as selected by the RDIV bits. The MCGLCLK is derived from
the FLL and the PLL is disabled in a low power state.
12.4.1.5
The PLL engaged external (PEE) mode is entered when all the following conditions occur:
In PLL engaged external mode, the MCGOUT clock is derived from the PLL clock which is controlled by
the external reference clock. The external reference clock which is enabled can be an external
crystal/resonator or it can be another external clock source The PLL clock frequency locks to a
multiplication factor, as selected by the VDIV bits, times the reference frequency, as selected by the RDIV
bits. If BDM is enabled then the MCGLCLK is derived from the DCO (open-loop mode) divided by two.
If BDM is not enabled then the FLL is disabled in a low power state.
194
•
•
•
•
•
•
•
•
•
CLKS bits are written to 10
IREFS bit is written to 0
PLLS bit is written to 0
RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz
LP bit is written to 0
CLKS bits are written to 00
IREFS bit is written to 0
PLLS bit is written to 1
RDIV bits are written to divide reference clock to be within the range of 1 MHz to 2 MHz
PLL Engaged External (PEE)
It is possible to briefly operate in FBE mode with an FLL reference clock
frequency that is greater than the specified maximum frequency. This can be
necessary in applications that operate in PEE mode using an external crystal
with a frequency above 5 MHz. Please see
from FEI to PEE Mode: External Crystal = 8 MHz, Bus Frequency = 8 MHz
for a detailed example.
MC9S08JM60 Series Data Sheet, Rev. 3
NOTE
12.5.2.4, “Example # 4: Moving
Freescale Semiconductor