MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 330

MC9S08JM60CLH

Manufacturer Part Number
MC9S08JM60CLH
Description
Manufacturer
Freescale
Datasheet

Specifications of MC9S08JM60CLH

Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
24MHz
Interface Type
SCI/SPI
Total Internal Ram Size
4KB
# I/os (max)
51
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
12-chx12-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
60KB
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S08JM60CLH
Manufacturer:
FREESCALE
Quantity:
2 500
Part Number:
MC9S08JM60CLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S08JM60CLH
Manufacturer:
FREESCALE
Quantity:
2 500
Part Number:
MC9S08JM60CLH
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MC9S08JM60CLHE
Manufacturer:
AZBIL
Quantity:
1 000
Development Support
When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD
chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU
into active background mode after reset. The specific conditions for forcing active background depend
upon the HCS08 derivative (refer to the introduction to this Development Support section). It is not
necessary to reset the target MCU to communicate with it through the background debug interface.
18.2.2
Communication Details
The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to
indicate the start of each bit time. The external controller provides this falling edge whether data is
transmitted or received.
BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data
is transferred MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if
512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress
when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU
system.
The custom serial protocol requires the debug pod to know the target BDC communication clock speed.
The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the
BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source.
The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams
show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but
asynchronous to the external host. The internal BDC clock signal is shown for reference in counting
cycles.
MC9S08JM60 Series Data Sheet, Rev. 3
330
Freescale Semiconductor

Related parts for MC9S08JM60CLH