MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 73

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

5.7.2
This register includes seven read-only status flags to indicate the source of the most recent reset. When a
debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will
be set. Writing any value except 0x55 and 0xAA in sequence to this register address causes the MCU reset
with the source of COP. The reset state of these bits depends on what caused the MCU to reset.
Freescale Semiconductor
1
Any other
IRQMOD
Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding
to sources that are not active at the time of reset will be cleared.
IRQACK
IRQIE
Field
reset:
Field
POR
POR
LVR:
PIN
2
1
0
7
6
W
R
U = Unaffected by reset
System Reset Status Register (SRS)
IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.
IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt
request.
0 Interrupt request when IRQF set is disabled (use polling).
1 Interrupt requested whenever IRQF = 1.
IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
detection. See
0 IRQ event on falling/rising edges only.
1 IRQ event on falling/rising edges and low/high levels.
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVR threshold.
0 Reset not caused by POR.
1 POR caused reset.
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
POR
U
1
0
7
Table 5-2. IRQSC Register Field Descriptions (continued)
Section 5.5.2.2, “Edge and Level
PIN
(1)
0
0
6
Writing any value to SRS address clears COP watchdog timer.
Table 5-3. SRS Register Field Descriptions
Figure 5-3. System Reset Status (SRS)
MC9S08JM60 Series Data Sheet, Rev. 3
COP
(1)
0
0
5
ILOP
(1)
0
0
4
Sensitivity,” for more details.
Description
Description
Chapter 5 Resets, Interrupts, and System Configuration
0
0
0
0
3
LOC
(1)
0
0
2
LVD
1
1
0
1
—
0
0
0
0
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