MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 287

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

and influences the way the main counter operates. (In CPWM mode, the counter changes to an up/down
mode rather than the up-counting mode used for general purpose timer functions.)
The following sections describe the main counter and each of the timer operating modes (input capture,
output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and
interrupt activity depend upon the operating mode, these topics will be covered in the associated mode
explanation sections.
16.4.1
All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section
discusses selection of the clock source, end-of-count overflow, up-counting vs. up/down counting, and
manual counter reset.
16.4.1.1
The 2-bit field, CLKSB:CLKSA, in the timer status and control register (TPMxSC) selects one of three
possible clock sources or OFF (which effectively disables the TPM). See
CLKSB:CLKSA=0:0 so no clock source is selected, and the TPM is in a very low power state. These
control bits may be read or written at any time and disabling the timer (writing 00 to the CLKSB:CLKSA
field) does not affect the values in the counter or other timer registers.
The bus rate clock is the main system bus clock for the MCU. This clock source requires no
synchronization because it is the clock that is used for all internal MCU activities including operation of
the CPU and buses.
In MCUs that have no PLL or the PLL is not engaged, the fixed system clock source is the same as the
bus-rate-clock source, and it does not go through a synchronizer. When a PLL is present and engaged, a
synchronizer is required between the crystal divided-by two clock source and the timer counter so counter
transitions will be properly aligned to bus-clock transitions. A synchronizer will be used at chip level to
synchronize the crystal-related source clock to the bus clock.
The external clock source may be connected to any TPM channel pin. This clock source always has to pass
through a synchronizer to assure that counter transitions are properly aligned to bus clock transitions. The
bus-rate clock drives the synchronizer; therefore, to meet Nyquist criteria even with jitter, the frequency
of the external clock source must not be faster than the bus rate divided-by four. With ideal clocks the
external clock can be as fast as bus clock divided by four.
Freescale Semiconductor
Counter
Counter Clock Source
CLKSB:CLKSA
00
01
10
11
Table 16-7. TPM Clock Source Selection
MC9S08JM60 Series Data Sheet, Rev. 3
No clock selected (TPM counter disabled)
TPM Clock Source to Prescaler Input
Fixed system clock
External source
Bus rate clock
Table
16-3. After any MCU reset,
Timer/PWM Module (S08TPMV3)
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