MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 259

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Any switching between 8- and 16-bit data transmission length (controlled by SPIMODE bit) in master
mode will abort a transmission in progress, force the SPI system into idle state, and reset all status bits in
the SPIxS register. To initiate a transfer after writing to SPIMODE, the SPIxS register must be read with
SPTEF = 1, and data must be written to SPIxDH:SPIxDL in 16-bit mode (SPIMODE = 1) or SPIxDL in
8-bit mode (SPIMODE = 0).
In slave mode, user software should write to SPIMODE only once to prevent corrupting a transmission in
progress.
15.4.5
To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI
system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock
formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses
between two different clock phase relationships between the clock and data.
Figure 15-13
figure, the eight bit times are shown for reference with bit 1 starting at the first SPSCK edge and bit 8
ending one-half SPSCK cycle after the sixteenth SPSCK edge. The MSB first and LSB first lines show the
order of SPI data bits depending on the setting in LSBFE. Both variations of SPSCK polarity are shown,
but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The
SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI
waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO
output from a slave. The SS OUT waveform applies to the slave select output from a master (provided
MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start
of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform
applies to the slave select input of a slave.
Freescale Semiconductor
SPI Clock Formats
shows the clock formats when SPIMODE = 0 (8-bit mode) and CPHA = 1. At the top of the
Data can be lost if the data length is not the same for both master and slave
devices.
MC9S08JM60 Series Data Sheet, Rev. 3
NOTE
Serial Peripheral Interface (S08SPI16V1)
259