MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 304

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Universal Serial Bus Device Controller (S08USBV1)
17.3.6
The INTENB contains enabling bits for each of the interrupt sources within the USB module. Setting any of these
bits will enable the respective interrupt source in the INTSTAT register. This register will contain the value of 0x00
after a reset, i.e. all interrupts disabled.
304
USBRSTF
ERRORF
RESUME
TOKDNE
SOFTOK
SLEEP
Reset
STALL
Field
Field
1
0
7
5
4
3
2
W
R
STALL
Interrupt Enable Register (INTENB)
Error Flag — This bit is set when any of the error conditions within the ERRSTAT register has occurred. The
firmware must then read the ERRSTAT register to determine the source of the error.
0 No error conditions within the ERRSTAT register have been detected
1 Error conditions within the ERRSTAT register have been detected
USB Reset Flag —This bit is set when the USB module has decoded a valid USB reset. When asserted, this bit
will inform the MCU to automatically write 0x00 to the address register and to enable endpoint 0. USBRSTF is
set once a USB reset has been detected for 2.5 μs. It will not be asserted again until the USB reset condition has
been removed, and then reasserted.
0 No USB reset observed
1 USB reset detected
STALL Interrupt Enable — Setting this bit will enable STALL interrupts.
0 Interrupt disabled
1 Interrupt enabled
RESUME Interrupt Enable — Setting this bit will enable RESUME interrupts.
0 Interrupt disabled
1 Interrupt enabled
SLEEP Interrupt Enable — Setting this bit will enable SLEEP interrupts.
0 Interrupt disabled
1 Interrupt enabled
TOKDNE Interrupt Enable — Setting this bit will enable TOKDNE interrupts.
0 Interrupt disabled
1 Interrupt enabled
SOFTOK Interrupt Enable — Setting this bit will enable SOFTOK interrupts.
0 Interrupt disabled
1 Interrupt enabled
0
7
0
0
6
Table 17-9. INTSTAT Field Descriptions (continued)
Figure 17-9. Interrupt Enable Register (INTENB)
Table 17-10. INTENB Field Descriptions
RESUME
MC9S08JM60 Series Data Sheet, Rev. 3
0
5
SLEEP
0
4
Description
Description
TOKDNE
3
0
SOFTOK
0
2
ERROR
Freescale Semiconductor
0
1
USBRST
0
0