MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 169
MC9S08JM60CLH
Manufacturer Part Number
MC9S08JM60CLH
Description
Manufacturer
Freescale
Datasheet
1.MC9S08JM60CLH.pdf
(388 pages)
Specifications of MC9S08JM60CLH
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
24MHz
Interface Type
SCI/SPI
Total Internal Ram Size
4KB
# I/os (max)
51
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
12-chx12-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
60KB
Lead Free Status / RoHS Status
Compliant
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11.3.5
Freescale Semiconductor
Reset
BUSY
ARBL
RXAK
Field
IAAS
SRW
IICIF
TCF
7
6
5
4
2
1
0
W
R
IIC Data I/O Register (IICD)
Transfer Complete Flag. This bit is set on the completion of a byte transfer. This bit is only valid during or
immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by reading the
IICD register in receive mode or writing to the IICD in transmit mode.
0 Transfer in progress
1 Transfer complete
Addressed as a Slave. The IAAS bit is set when the calling address matches the programmed slave address or
when the GCAEN bit is set and a general call is received. Writing the IICC register clears this bit.
0 Not addressed
1 Addressed as a slave
Bus Busy. The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is set
when a start signal is detected and cleared when a stop signal is detected.
0 Bus is idle
1 Bus is busy
Arbitration Lost. This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared
by software by writing a 1 to it.
0 Standard bus operation
1 Loss of arbitration
Slave Read/Write. When addressed as a slave, the SRW bit indicates the value of the R/W command bit of the
calling address sent to the master.
0 Slave receive, master writing to slave
1 Slave transmit, master reading from slave
IIC Interrupt Flag. The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by
writing a 1 to it in the interrupt routine. One of the following events can set the IICIF bit:
0 No interrupt pending
1 Interrupt pending
Receive Acknowledge. When the RXAK bit is low, it indicates an acknowledge signal has been received after
the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge
signal is detected.
0 Acknowledge received
1 No acknowledge received
0
7
• One byte transfer completes
• Match of slave address to calling address
• Arbitration lost
0
6
Figure 11-7. IIC Data I/O Register (IICD)
MC9S08JM60 Series Data Sheet, Rev. 3
Table 11-6. IICS Field Descriptions
0
5
0
4
Description
DATA
3
0
0
2
0
1
0
0
169
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