MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 251

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
SPIMODE
MODFEN
BIDIROE
SPISWAI
Reset
SPMIE
SPC0
Field
7
6
4
3
1
0
W
R
SPMIE
SPI Match Interrupt Enable — This is the interrupt enable for the SPI receive data buffer hardware match
(SPMF) function.
0 Interrupts from SPMF inhibited (use polling).
1 When SPMF = 1, requests a hardware interrupt.
SPI 8- or 16-bit Mode — This bit allows the user to select either an 8-bit or 16-bit SPI data transmission length.
In master mode, a change of this bit will abort a transmission in progress, force the SPI system into idle state,
and reset all status bits in the SPIxS register. Refer to section
details.
0 8-bit SPI shift register, match register, and buffers.
1 16-bit SPI shift register, match register, and buffers.
Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or
effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to
Table 15-2
0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1,
BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin.
Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO
(SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect.
0 Output driver disabled so SPI data I/O pin acts as an input
1 SPI I/O pin enabled as an output
SPI Stop in Wait Mode — This bit is used for power conservation while in wait.
0 SPI clocks continue to operate in wait mode
1 SPI clocks stop when the MCU enters wait mode
SPI Pin Control 0 — This bit enables bidirectional pin configurations as shown in
0 SPI uses separate pins for data input and data output.
1 SPI configured for single-wire bidirectional operation.
0
7
= Unimplemented or Reserved
for details)
SPIMODE
0
6
Table 15-3. SPIxC2 Register Field Descriptions
Figure 15-6. SPI Control Register 2 (SPIxC2)
MC9S08JM60 Series Data Sheet, Rev. 3
0
0
5
MODFEN
0
4
Description
BIDIROE
3
0
Section 15.4.4, “Data Transmission
Serial Peripheral Interface (S08SPI16V1)
0
0
2
Table
SPISWAI
15-4.
0
1
Length,” for
SPC0
0
0
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