MC9S08JM60CLH Freescale, MC9S08JM60CLH Datasheet - Page 171

• Manufacturer Part Number: MC9S08JM60CLH
• Manufacturer: Freescale

Specifications of MC9S08JM60CLH

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

11.4
This section provides a complete functional description of the IIC module.
11.4.1
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. A logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts:
The stop signal should not be confused with the CPU stop instruction. The IIC bus system communication
is described briefly in the following sections and illustrated in
11.4.1.1
When the bus is free, no master device is engaging the bus (SCL and SDA lines are at logical high), a
master may initiate communication by sending a start signal. As shown in
defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new
data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle
states.
Freescale Semiconductor
•
•
•
•
SCL
SDA
SCL
SDA
Start signal
Slave address transmission
Data transfer
Stop signal
Functional Description
Signal
Signal
Start
Start
IIC Protocol
Start Signal
msb
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
msb
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
1
1
2
2
Calling Address
Calling Address
3
3
4
4
5
5
Figure 11-9. IIC Bus Transmission Signals
MC9S08JM60 Series Data Sheet, Rev. 3
6
6
7
7
Read/
Read/
Write
Write
lsb
lsb
8
8
Ack
Ack
Bit
9
Bit
9
XX
Repeated
XXX
Signal
Start
msb
msb
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
D7
1
1
Figure
D6
2
2
New Calling Address
D5
3
3
11-9.
Data Byte
D4
4
4
D3
Figure
5
5
D2
6
6
11-9, a start signal is
D1
7
7
Read/
Write
lsb
lsb
D0
8
8
Ack
No
Bit
Ack
No
9
Bit
9
Signal
Stop
Signal
Stop
171