r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1014

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

20. Graphics Data Translation Accelerator (GDTA)
20.3.6
DRCL_CTL is in the GDTA common register block and specifies data alignment of CL input
data.
Note: For details of data alignment conversion patterns, refer to section 20.6, Data Alignment.
Rev.1.00 Jan. 10, 2008 Page 984 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 5
4
3, 2
1, 0
R/W:
R/W:
BIt:
BIt:
GA CL Input Data Alignment Register (DRCL_CTL)
Bit Name
⎯
DCLR_DTAM 0
DCLR_DTSA 0
DCLR_DTUA 0
31
15
⎯
⎯
⎯
⎯
0
0
30
⎯
⎯
14
⎯
⎯
0
0
29
⎯
⎯
13
⎯
⎯
0
0
Initial
Value
All 0
28
12
⎯
⎯
⎯
⎯
0
0
R/W
⎯
R/W
R/W
R/W
27
11
⎯
⎯
⎯
⎯
0
0
26
10
⎯
⎯
⎯
⎯
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Specifies data alignment conversion mode.
0: Data alignment is performed using an endian signal
1: Data alignment is performed using the DRCL_CTL
Specifies the data size for data alignment conversion.
00: No conversion
01: 64 bits
10: 32 bits
11: 16 bits
Specifies the unit for data alignment conversion.
00: No conversion
01: 8 bits
10: 16 bits
11: 32 bits
register setting
25
⎯
⎯
⎯
⎯
0
9
0
24
⎯
⎯
⎯
⎯
0
8
0
23
⎯
⎯
⎯
⎯
0
7
0
22
⎯
⎯
⎯
⎯
0
6
0
21
⎯
⎯
⎯
⎯
0
5
0
DCLR_
DTAM
R/W
20
⎯
⎯
0
4
0
DCLR_DTSA
R/W
19
⎯
⎯
0
3
0
R/W
18
⎯
⎯
0
2
0
DCLR_DTUA
R/W
17
⎯
⎯
0
1
0
R/W
16
⎯
⎯
0
0
0