r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 974

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

19. Display Unit (DU)
Table 19.11 RGB888 Bit Configuration in Each Display Data Format
When the format of display data for α blending or EOR operation is 8 bits/pixel, after selection in
advance of the color palette to be used, the α blending or EOR operation on/off should be
specified. At this time, when both planes for α blending or for EOR operation have the same color
palette selected (color palette contention), only the specified plane is displayed, with no α
blending or EOR operation performed. When display of all lower planes is turned off, the
specified plane is displayed. That is, blending or EOR operation of the specified plane with the
display data specified in BPOR is not performed.
α Blending: In α blending, blending processing is performed according to the alpha (α) value set
by the PnALPHA bits in PnALPHAR, the alpha (α) value set by the blend ratio bits in the color
palette, or the alpha (α) value of the input display data.
Notes: 1. In the above formula, the blending result, α, the specified plane, and the lower plane
Rev.1.00 Jan. 10, 2008 Page 944 of 1658
REJ09B0261-0100
Data Format
8 bits/pixel
16 bits/pixel
ARGB
YC→RGB
Plane with priority 1
Plane with priority 2
Plane with priority 3
Plane with priority 4
Plane with priority 5
Plane with priority 6
The priority is set in DPPR.
2. When 0 is set as the alpha value, only the lower plane is displayed.
3. Approximation compensation is not performed. Alpha value is equal to H'FF, specified
Blending result = (α × specified plane + (H'100-α) × lower plane)/H'100
Figure 19.5 Plane Processing Sequence in α Blending and EOR Operation
are all given as 8-bit data.
plane is equal to H'FF and lower plane equal to H’00, and then the result is H'FE.
R (8 bits)
R (6 bits)
R (5 bits)
R (5 bits)
R (8 bits)
0
0
Plane PnSPIM with priority 5
0
0
0
0
0
0
Plane PnSPIM with priority 4
G (8 bits)
G (6 bits)
G (6 bits)
G (5 bits)
G (8 bits)
Plane PnSPIM with priority 3
0
Plane PnSPIM with priority 2
0
0
0
0
0
0
Plane PnSPIM with priority 1
B (8 bits)
B (6 bits)
B (5 bits)
B (5 bits)
B (8 bits)
Superposition
processing circuit
Output display data
0
0
0
0
0
0
0
0