r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 763

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r8a77850anbg

Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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The CPG generates clocks provided to the internal and external bus interfaces of the SH7785, and
controls power-down mode. The CPG consists of a crystal oscillator circuit, PLLs, dividers, and
the control unit.
15.1
The CPG has the following features.
• Generates SH7785 internal clocks*
• Generates SH7785 external clocks
• Clock operating modes
• Controls power-down mode
Figure 15.1 shows a block diagram of the CPG.
Note: * For description of the clock used by each module, see the sections on individual
Generates the CPU clock (Ick) used in the CPU, FPU, cache, and TLB; the SuperHyway clock
(SHck) used in the SuperHyway, the GDTA clock (GAck) used in the graphic data translation
accelerator, the DU clock (DUck) used in the display unit; the peripheral clock (Pck) used in
the interface with on-chip peripheral modules; and the RAM clock (Uck) used in URAM
Generates the bus clock (Bck) used in the interface with the external devices, and the DDR
clock (DDRck) for the memory clock used in the DBSC2.
Selects a crystal resonator or an external clock input for the clock input to the CPG
Can stop the CPU in sleep mode and specific modules in module standby mode. For details,
see section 17, Power-Down Mode.
Features
modules.
Section 15 Clock Pulse Generator (CPG)
Rev.1.00 Jan. 10, 2008 Page 733 of 1658
15. Clock Pulse Generator (CPG)
REJ09B0261-0100

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