r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1043

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

20.4
20.4.1
By writing 1 to the CL_EN bit in GACER, registers in the CL register unit can be accessed. After
setting, as initial values, the input frame width/height, input padding size, output padding size,
operating mode (and, in ARGB conversion mode, the palette pointer setting), data written in
succession to CLCF is received, and upon receiving four command parameters (input Y/U/V
pointers, output pointer), processing is begun. In processing, data for one input frame as defined
by the settings (width vs. height) is read, and by setting the CL_MD bit in CLCR, YUYV
conversion or ARGB conversion is performed within the module. Processing is performed in
single frame units, and one frame's worth of converted data is transmitted to the output destination.
The CL can store two commands (in register CLCF) and does not accept the command for the next
frame when two commands are already stored (command FIFO full). A judgment as to whether
processing has ended can be made by using either an interrupt or the CL_END bit in GACISR.
(1)
The following shows an outline of the YUYV conversion specification.
U pointer
Y pointer
V pointer
Output
pointer
Input
Input
Input
Overview of YUYV Conversion Functions
Y10 U1
U0 U1
Y0 Y1
Y4 Y5 Y6 Y7
U4 U5
V0 V1
Y0 U0 Y1 V0
Y2 U1 Y3 V1
Y4 U2 Y5 V2
Y6 U3 Y7 V3
Y8 U0
** ** ** **
** ** ** **
Y8 Y9
** ** ** **
** ** ** **
** ** ** **
** ** ** **
V4 V5
** ** ** **
** ** ** **
DDR2-SDRAM
GDTA Operation
Explanation of CL Operation
. .
.
. .
.
. .
.
. .
.
...
...
U2 U3
Y2 Y3
V2 V3
Y9 V0
...
...
External memory
connected to the
local bus
(1) Input data
reading
Figure 20.3 YUYV Conversion Functions
Y16 U4
Y24 U8
Y32 U1
Y0
Y8
U0
U0
Y17
Y25
Y33
Y1
Y9
V12
V0
V0
V4
V8
(3) Output data writing (including output padding data)
Y34 U13
Y10 U1
Y18 U5
Y26 U9
Y2
(2) Rearrangement (with output padding)
U1
Frame width (8 pixels in this figure)
Y11
Y19
Y27
Y35
Y3
20. Graphics Data Translation Accelerator (GDTA)
V13
V1
V1
V5
V9
Display image
Y12 U2
Y20 U6
Y28 U10
Y36 U14
Y4
Rev.1.00 Jan. 10, 2008 Page 1013 of 1658
U2
Depending on the specified width and padding size,
there may exist either one or neither of "padding data
for output" and "padding data not for output".
In the example of this figure, H'8 is set in CLIWR
and H'30 is set in CLOPR.
Y13
Y21
Y29
Y37
Y5
V10
V14
V2
V2
V6
Y14 U3
Y22 U7
Y30 U11
Y38 U15
Y6
U3
Converted data output order
Output padding size (= 48 bytes)
Y15
Y23
Y31
Y39
For output
(= 16 bytes)
Y7
REJ09B0261-0100
V11
V15
V3
V3
V7
Not for output
(= 32 bytes)