r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 579

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

5. The SDRAM configuration setting register (DBCONF), SDRAM timing register 0 (DBTR0),
6. By writing to the DDRPAD frequency setting register DBFREQ, DLL settings are made.
7. Write to the DDRPAD DIC, ODT, OCD setting register DBDICODTOCD. Values to be
8. Use the CMD bits in the SDRAM command control register (DBCMDCNT) to set the MCKE
9. Write to DBCMDCNT to issue a REF (auto-refresh) command.
10. Set the ACEN bit in the SDRAM operation enable register (DBEN) to 1 (access enabled).
11. Set the SDRAM refresh control registers 1 and 2 (DBRFCNT1 and DBRFCNT2).
12. Set the ARFEN bit in the SDRAM refresh control register 0 (DBRFCNT0) to 1 (automatic
12.5.11 Method for Securing Time Required for Initialization, Self-Refresh Cancellation,
When using DBSC2 register settings to set initialization, cancel self-refresh and the like, it is
necessary to wait a time stipulated by the SDRAM specifications. One example of this waiting is
the method used to read the DBSC2 status register (DBSTATE). Upon executing reading of the
DBSC2 status register (DBSTATE), a minimum of 8 cycles of the memory clock elapse. If
operation is at 300 MHz, then approximately 26 ns elapses in a single DBSTATE read operation.
This can be utilized to secure the required time, by repeating read access the necessary number of
times.
12.5.12 Regarding the Supported Clock Ratio
The only clock ratio supported by the DBSC2 is a ratio of 1:1 between the SuperHyway clock and
the DDR clock. Clock ratios other than 1:1 are not supported.
SDRAM timing register 1 (DBTR1), and SDRAM timing register 2 (DBTR2) should be set.
A. Set DLLRST = 0.
B. Set the FREQ bits to the DDRPAD frequency.
C. After setting DLLRST = 1, the software waits for the DLL stabilization time of 100 μs or
written should match values set in SDRAM EMRS(1).
signal to high level, and have the software wait for the time, requested by the respective
memory manufacturers, from cancellation of the self-refresh state until issue of a non-read
command (time tXSNR).
issue of auto-refresh enabled). Thereafter, normal access is possible.
more required by DDRPAD.
etc.
Rev.1.00 Jan. 10, 2008 Page 549 of 1658
12. DDR2-SDRAM Interface (DBSC2)
REJ09B0261-0100