r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 398

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 368 of 1658
REJ09B0261-0100
Bit
26
25
24
23 to 20 DACKBST
Bit Name
DPUP
⎯
OPUP
[3:0]
Initial
Value
0
0
0
All 0
R/W
R/W
R
R/W
R/W
Description
Data Pin Pull-Up Resistor Control
Specifies the pull-up resistor state of the data pins (D63
to D0). This bit is initialized at a power-on reset. The
pins are not pulled up when access is performed or
when the bus is released, even if the pull-up resistor is
on.
0: Some cycles of the pull-up resistors of the data pins
1: Pull-up resistors of the data pins (D63 to D0) are off.
Note: * When data pin pull-up is necessary, it is
Reserved
This bit is always read as 0. The write value should
always be 0.
Control Output Pin Pull-Up Resistor Control
Specifies the pull-up resistor state (A25 to A0, BS, CSn,
RD, WE, R/W, CE2A, and CE2B) when the control
output pins are high-impedance. This bit is initialized at
a power-on reset.
0: Pull-up resistors for control output pins (A25 to A0,
1: Pull-up resistors for control output pins (A25 to A0,
DACKBST3 to DACKBST0
0: DACKn signals asserted in synchronization with the
1: DACKn signals remain asserted from the start to the
These bits can be set to 1 only when the memory type
of the DACK output area in the corresponding DMA
transfer channel is set to PCMCIA interface. In other
cases, these bits should be cleared to 0.
The pins corresponding to each bits are as follows.
DACKBST[3]: DACK3
DACKBST[2]: DACK2
DACKBST[1]: DACK1
DACKBST[0]: DACK0
end of burst transfer when DMA transfer is performed
in burst mode
bus cycle (n = 0 to 3)
BS, CSn, RD, WE, R/W, CE2A, and CE2B) are on
BS, CSn, RD, WE, R/W, CE2A, and CE2B) are off
(D63 to D0) are turned on before and after a
memory access.*
recommended to connect a pull-up resistor
externally.