r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1168

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

22. Serial I/O with FIFO (SIOF)
Table 22.12 Conditions to Issue Receive Request
Note:
The number of stages of the FIFO is always sixteen even if the data area or empty area exceeds the
FIFO size. Accordingly, an overflow error or underflow error occurs if data area or empty area
exceeds sixteen FIFO stages.
The FIFO transmit or receive request is canceled when the above condition is not satisfied even if
the FIFO is not empty or full.
(3)
The number of FIFO stages used in transmission and reception is indicated by the following
register.
• Transmit FIFO: The number of empty FIFO stages is indicated by the TFUA4 to TFUA0 bits
• Receive FIFO: The number of valid data stages is indicated by the bits RFUA4 to RFUA0 bits
Rev.1.00 Jan. 10, 2008 Page 1138 of 1658
REJ09B0261-0100
RFWM2 to
RFWM0
000
100
101
110
111
in SIFCTR.
in SIFCTR.
The above indicates possible data numbers that can be transferred by the CPU or DMAC.
Number of FIFOs
*
The number of requested stages is the number of stages in transmit/receive FIFO.
Number of
Requested Stages*
1
4
8
12
16
Receive Request
Valid data is 1 stage or more
Valid data is 4 stages or more
Valid data is 8 stages or more
Valid data is 12 stages or more
Valid data is 16 stages
Used Areas
Smallest
Largest