r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1024

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

20. Graphics Data Translation Accelerator (GDTA)
20.3.15 CL Frame Width Setting Register (CLWR)
CLWR is in the CL register block and sets the input image width in pixel units.
Notes: 1. CL processing is prohibited when the setting is 0.
Rev.1.00 Jan. 10, 2008 Page 994 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 12 ⎯
11 to 0
R/W:
R/W:
BIt:
BIt:
2. Addition is performed taking that 1 pixel = 1 byte.
3. CLWR (bytes) + CLIYPR (bytes) should be 32 bytes × n (n: an integer greater than 0)
4. CLWR (bytes)/2 + CLUVPR (bytes) should be 32 bytes × n (n: an integer greater than
Bit Name
CL_W
0)
31
15
⎯
⎯
⎯
⎯
0
0
30
⎯
⎯
14
⎯
⎯
0
0
29
⎯
⎯
13
⎯
⎯
0
0
Initial
Value
All 0
All 0
28
12
⎯
⎯
⎯
⎯
0
0
R/W
R/W
⎯
R/W
27
11
⎯
⎯
0
0
R/W
26
10
⎯
⎯
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Frame width setting
Should be set in pixel units.
Value set should be 2 × n (n: an integer greater than 0)
R/W
25
⎯
⎯
0
9
0
R/W
24
⎯
⎯
0
8
0
R/W
23
⎯
⎯
0
7
0
R/W
22
⎯
⎯
0
6
0
CL_W
R/W
21
⎯
⎯
0
5
0
R/W
20
⎯
⎯
0
4
0
R/W
19
⎯
⎯
0
3
0
R/W
18
⎯
⎯
0
2
0
R/W
17
⎯
⎯
0
1
0
R/W
16
⎯
⎯
0
0
0