r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 373

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

10.7
10.7.1
When ICR0.LVLMODE is 0, IRL interrupt requests and level detection IRQ interrupt requests
that the INTC retains should be cleared in the interrupt handling routine because the CPU detects
after accepting interrupts. The IRQ interrupt sources (INTREQ) should also be cleared.
Canceling the IRL interrupt request and level detection IRQ interrupt request that the CPU accepts
should be notified to the external device in the interrupt handling routine. For example, output the
data that can identify the accepted level and pins to the GPIO pin, or read the specific address. In
this case, write to the GPIO register and the local bus space, and read the same address
continuously.
To clear an interrupt request that is retained in the INTC, the wait time that the CPU detects the
cleared interrupt request is required. To guarantee the wait time, write to INTMSK0, INTMSK1,
INTMSKCLR0, and INTMSKCLR1, and read from INTMSK0 continuously.
Usage Notes
Example of Handing Routine of IRL Interrupts and Level Detection IRQ
Interrupts when ICR0.LVLMODE = 0
request holding in the detection circuit
Instruct the external device to cancel
the IRQ/IRL level interrupt request by
using the GPIO output or writing to an
address in the local bus
Wait until the interrupt request signal
input on the IRL/IRQ pin is negated
and the INTC detects the negation
(at least 8 bus-clock cycles are
required)
and clear the IRQ interrupt source
Clear the IRQ/IRL level interrupt
level-encoded interrupt handling
Start of IRQ level-sense or IRL
Figure 10.6 Example of Interrupt Handling Routine
End of IRQ/IRL level
Interrupt handling
interrupt handling
1) Write to the GPIO register or local
2) Read from the address that has been
1) Set the corresponding bit in
2) Set the corresponding bit in
3) Read INTMSK0/1.
bus space.
written to.
INTMSK0/1 to 1.
INTMSKCLR0/1 to 1.
Rev.1.00 Jan. 10, 2008 Page 343 of 1658
10. Interrupt Controller (INTC)
REJ09B0261-0100