r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 401

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

11.4.3
CSnBCR are 32-bit readable/writable registers that specify the bus width for area n (n = 0 to 6),
idle mode between cycles, burst ROM setting and memory types.
Some types of memory continue to drive the data bus immediately after the read signal is turned
off. Therefore, data buses may collide with each other when different memory areas are accessed
consecutively or memory writing is performed immediately after it is read. This LSI automatically
inserts idle cycles as specified with CSnBCR when the data buses may collide. In the idle cycles,
CSn, RD, WEn, CE2A, CE2B, BS and R/W are set to high, and the data bus is not driven.
CSnBCR is initialized to H'7777 77F0 at a power-on reset, but is not initialized by a manual reset.
Initial value:
Initial value:
Bit
31
R/W:
R/W:
BIt:
BIt:
CSn Bus Control Register (CSnBCR)
Bit Name
⎯
Note: * Bits SZ and MPX in CS0BCR are read-only.
31
15
⎯
⎯
R
R
0
0
R/W
R/W
30
14
1
1
IWRRS
IWW
R/W
R/W
29
13
1
1
Initial
Value
0
R/W
R/W
28
12
1
1
R/W
R/W
R
27
⎯
11
R
0
0
BST
R/W
R/W
26
10
1
1
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
IWRWD
R/W*
R/W
25
1
9
1
SZ*
R/W*
R/W
24
1
8
1
RDSPL
R/W
23
⎯
R
0
7
1
Rev.1.00 Jan. 10, 2008 Page 371 of 1658
R/W
R/W
22
1
6
1
11. Local Bus State Controller (LBSC)
IWRWS
R/W
R/W
BW
21
1
5
1
R/W
R/W
20
1
4
1
MPX*
R/W*
19
⎯
R
0
3
0
REJ09B0261-0100
R/W
R/W
18
1
2
0
IWRRD
TYPE
R/W
R/W
17
1
1
0
R/W
R/W
16
1
0
0