r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 371

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

Table 10.15 shows response time. The response time is from the interrupt exception handling to
the start of fetching the first instruction in exception handling routine. In this case, suppose that
the setting values of the following registers that enable or disable interrupt, INTMSK0,
INTMSK1, INTMSK2, INT2MSKR, and INT2GPIC, are changed from the interrupt disable state
to the interrupt enable state.
Table 10.15 Response Time after Changing the Value of Interrupt Enable/Disable Registers
Legend:
Icyc:
Scyc: Period of one SuperHyway clock cycle
Bcyc: Period of one bus clock cycle
Pcyc: Period of one peripheral clock cycle
S:
Note:
Item
Priority determination time*
Wait time until the CPU
finishes the current sequence
Interval from the start of
interrupt exception handling
(saving SR and PC) until a
SuperHyway bus request is
issued to fetch the first
instruction of the exception
handling routine
Response
time
Period of one CPU clock cycle
Number of instruction execution states
*
When INTMSKCLR0, INTMSKCLR1, INTMSKCLR2, and INT2MSKCLR are written to,
INTMSK0, INTMSK1, INTMSK2, and INTMSKR enable an interrupt by clearing the
mask bits in INTMSK0, INTMSK1, INTMSK2, and INTMSKR. The priority determination
times in table 10.15 are the values after the values of INTMSK0, INTMSK1, INTMSK2,
and INT2MSKR are changed.
Total
(Interrupt Disabled → Interrupt Enabled)
INTMSK1
1Pcyc
S-1 (≥ 0) × Icyc
11Icyc + 1Scyc
(S + 10) Icyc
+ 1Scyc
+ 1Pcyc
IRL
INTMSK2
8Bcyc +
2Pcyc
(S + 10) Icyc
+ 1Scyc
+ 8Bcyc
+ 2Pcyc
Number of States
IRQ
INTMSK0
1Pcyc
(S + 10) Icyc
+ 1Scyc
+ 1Pcyc
Rev.1.00 Jan. 10, 2008 Page 341 of 1658
Peripheral
Modules
INT2MSKR,
INT2GPIC
4Pcyc
(S + 10) Icyc
+ 1Scyc
+ 4Pcyc
10. Interrupt Controller (INTC)
Remarks
Registers that
enable/disable
interrupts
REJ09B0261-0100