r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 370

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r8a77850anbg

Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet

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10. Interrupt Controller (INTC)
10.6
Table 10.14 shows response time. The response time is the interval from generation of an interrupt
request until the start of interrupt exception handling and until fetching of the first instruction of
the exception handling routine.
Table 10.14 Interrupt Response Time
Legend:
Icyc:
Scyc: Period of one SuperHyway clock cycle
Bcyc: Period of one bus clock cycle
Pcyc: Period of one peripheral clock cycle
S:
Rev.1.00 Jan. 10, 2008 Page 340 of 1658
REJ09B0261-0100
Item
Priority
determination time
Wait time until the
CPU finishes the
current sequence
Interval from the
start of interrupt
exception handling
(saving SR and PC)
until a SuperHyway
bus request is issued
to fetch the first
instruction of the
exception handling
routine
Response
time
Period of one CPU clock cycle
Number of instruction execution states
Interrupt Response Time
Total
NMI
6Bcyc +
2Pcyc
(S + 10) Icyc
+ 1Scyc
+ 5Bcyc
+ 2Pcyc
IRL
8Bcyc +
2Pcyc
(S + 10) Icyc
+ 1Scyc
+ 8Bcyc
+ 2Pcyc
Number of States
IRQ
4Bcyc +
2Pcyc
S-1 (≥ 0)
× Icyc
11Icyc
+ 1Scyc
(S + 10) Icyc
+ 1Scyc
+ 4Bcyc
+ 2Pcyc
Other than
GPIO/PCIC
5Pcyc
(S + 10) Icyc
+ 1Scyc
+ 5Pcyc
Peripheral Modules
GPIO/PCIC
7Pcyc
(S + 10) Icyc
+ 1Scyc
+ 7Pcyc
Remarks

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